As MOSFET (metal oxide semiconductor field effect transistor) gate length decreases, the unit power gain frequency (fMAX) degrades due to the up-scaling of parasitics.
U.S. Pat. No. 5,268,330 to Givens et al. describes a process for improving sheet resistance of an integrated circuit device gate.
U.S. Pat. No. 5,554,544 to Hsu describes a field edge method of manufacturing a T-gate LDD pocket device.
U.S. Pat. No. 5,739,066 to Pan describes a semiconductor processing method of forming a conductive gate or gate line over a substrate.
U.S. Pat. No. 6,063,675 to Rodder describes a method of forming a MOSFET using a disposable gate with a sidewall dielectric.
U.S. Pat. No. 5,943,560 to Chang et al. describes a method of fabricating a thin film transistor using ultrahigh vacuum chemical vapor deposition (UHV/CVD) and chemical mechanical polishing (CMP) systems.
U.S. Pat. No. 5,731,239 to Wong et al. describes a method of fabricating self-aligned silicide narrow gate electrodes for field effect transistors (FET) having low sheet resistance.